The Anti-Tamper Digital Clocks Diaries
The Anti-Tamper Digital Clocks Diaries
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SUMMARY An facet of the existing creation may perhaps reside in a method for detecting clock tampering. In the tactic a plurality of resettable delay line segments are supplied. Resettable hold off line segments concerning a resettable hold off line segment associated with a minimum hold off time as well as a resettable delay line section connected with a greatest delay time are Just about every affiliated with discretely rising delay periods.
A monotone signal is offered for the duration of a clock evaluate time frame connected to a clock. The monotone sign is delayed working with Each individual of the plurality of check here resettable delay line segments to make a respective plurality of delayed monotone signals. The clock is accustomed to trigger an Assess circuit that employs the plurality of delayed monotone indicators to detect a clock fault.
The next clock evaluate time frame addresses a distinct time than the initial clock Assess time frame, as might be enforced by an inverter 730. The next plurality of resettable delay line segments Every single delay the next monotone sign to make a respective next plurality of delayed monotone indicators. Resettable hold off line segments among a resettable hold off line section connected to a minimum delay time and also a resettable delay line section connected to a highest hold off time are each connected to discretely escalating delay situations. The Examine circuit is triggered because of the clock (e.g., EVAL) and employs the very first plurality of delayed monotone alerts or the second plurality of delayed monotone indicators to detect a clock fault. A multiplexer 760 could pick which of the first or second plurality of delayed monotone signals are active to become furnished to your Examine circuit.
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The present invention relates generally to detecting tampering With all the clock and/or source voltage of the processor.